With the Growing Popularity of System-on- Embedded Software-based Self-test for Programmable Core-based Designs

a-chip (SoC) architectures, demands for short time to market and rich functionality have driven design houses to adopt a new core-based SoC design flow. A core-based SoC incorporates multiple complex, heterogeneous components on a single piece of silicon; these can include digital, analog, mixed-signal, RF, micromechanical, and other kinds of systems. This blurring of the boundaries between different types of devices, together with rapidly increasing operational frequencies and shrinking feature sizes, has introduced a whole new set of testing challenges. Not only are high-speed testers costly, but also their performance is increasing more slowly than device speed. Thus, externally testing SoCs translates into increasing yield loss, because guardbanding to cover tester errors results in the loss of increasingly more good chips. Because digital logic testers cannot do precise analog testing, externally testing mixedsignal chips requires an even more expensive mixed-signal tester and a two-pass strategy. For some designs, testing the digital core involves pumping a vast amount of digital data through an analog interface; for these, neither of the two platforms would work. Built-in self-test (BIST) solutions eliminate the need for high-speed testers and can more accurately apply and analyze at-speed test signals on chip. Existing structural BIST techniques, such as scan-based BIST, offer good test quality but require additional dedicated test circuitry, so they incur nontrivial area, performance, and design time overhead. Moreover, structural BIST’s nonfunctional, high-switching random patterns consume much more power than normal system operation. Finally, to apply at-speed tests to detect timing-related faults, existing structural BIST must resolve various complex timing issues related to multiple clock domains, multiple frequencies, and test clock skews that are unique in test mode. A new paradigm, embedded software-based self-testing, could alleviate the problems of both external testers and structural BIST.1-3 In this strategy, sometimes called functional self-testing, the SoC’s programmable cores first undergo self-test by running an automatically synthesized test program that achieves high fault coverage. Next, the programmable core functions as a pattern generator and response analyzer to test on-chip buses, interfaces Embedded Software-Based Self-Test for Programmable Core-Based Designs Embedded Systems